Stacked memory cell utilizing negative differential resistance devices

ABSTRACT

A memory cell includes two negative differential resistance (NDR) field effect transistors (FETs) forming a bistable latch, and an access transistor for allowing data to be passed to and from the storage node formed by the bistable latch. By stacking the NDR-FETs and the access transistor in two or more layers, area requirements for the memory cell can be reduced, thereby enabling increased circuit density in an integrated circuit (IC) incorporating the memory cell.

CROSS REFERENCE TO RELATED APPLICATIONS Related Applications

The present application is a continuation-in-part of U.S. patentapplication Ser. No. 10/827,787, entitled “Method Of Making Memory CellUtilizing Negative Differential Resistance Devices” filed Apr. 19, 2004which is a divisional of U.S. patent application Ser. No. 10/029,077,entitled “Memory Cell Using Negative Differential Resistance FieldEffect Transistors” filed Dec. 21, 2001, now U.S. Pat. No. 6,724,655.

The present application is also related to the following applications,all of which are filed simultaneously with parent application Ser. No.10/029,077, and which are hereby incorporated by reference as if fullyset forth herein:

An application Ser. No. 10/028,084 entitled “INSULATED-GATE FIELD-EFFECTTRANSISTOR INTEGRATED WITH NEGATIVE DIFFERENTIAL RESISTANCE (NDR) FET”;Attorney Docket No. PROG 2001-1; and

An application Ser. No. 10/028,394 entitled “DUAL MODE FET & LOGICCIRCUIT HAVING NEGATIVE DIFFERENTIAL RESISTANCE MODE”; Attorney DocketNo. PROG 2001-3, now U.S. Pat. No. 6,518,589;

An application Ser. No. 10/028,089 entitled “CHARGE PUMP FOR NEGATIVEDIFFERENTIAL RESISTANCE TRANSISTOR” Attorney Docket No. PROG 2001-4, nowU.S. Pat. No. 6,594,193;

An application Ser. No. 10/028,085 entitled “IMPROVED NEGATIVEDIFFERENTIAL RESISTANCE FIELD EFFECT TRANSISTOR (NDR-FET) & CIRCUITSUSING THE SAME”; Attorney Docket No. PROG 2001-5; now U.S. Pat. No.6,559,470.

FIELD OF THE INVENTION

This invention generally relates to semiconductor memory devices andtechnology, and in particular to static random access memory (SRAM)devices.

BACKGROUND OF THE INVENTION

The rapid growth of the semiconductor industry over the past fourdecades has largely been enabled by continual advancements inmanufacturing technology which have allowed the size of the transistor,the basic building block in integrated circuits (ICs), to be steadilyreduced with each new generation of technology. As the transistor sizeis scaled down, the chip area required for a given circuit is reduced,so that more chips can be manufactured on a single silicon wafersubstrate, resulting in lower manufacturing cost per chip; circuitoperation speed also improves, because of reduced capacitance and highertransistor current density. State-of-the-art fabrication facilitiespresently manufacture ICs with minimum transistor feature size smallerthan 100 nm, so that microprocessor products with transistor countsapproaching 1 billion transistors per chip can be manufacturedcost-effectively. High-density semiconductor memory devices have alreadyreached the gigabit scale, led by dynamic random access memory (DRAM)technology. The DRAM memory cell consists of a single pass transistorand a capacitor (1T/1C), wherein information is stored in the form ofcharge on the capacitor. Although the DRAM cell provides the mostcompact layout (with area ranging between 4F² and 8F², where F is theminimum feature half-pitch defined by lithography), it requires frequentrefreshing (typically on the order of once per millisecond) because thecharge on the capacitor leaks away at a rate of approximately 10⁻¹⁵Amperes per cell. This problem is exacerbated by technology scaling,because the transistor leakage current increases with decreasing channellength, and also because a reduction in cell capacitance results in asmaller number of stored charge carriers, so that more frequentrefreshing is necessary. Thus, scaling of DRAM technology to much higherdensities presents significant technological challenges.

Static RAM (SRAM) does not require refreshing and is generally fasterthan DRAM (approaching 1 ns access times as compared to tens of ns forDRAM). However, the SRAM cell is more complex, requiring either fourn-channel metal-oxide-semiconductor field-effect transistors (MOSFETs)and two p-channel MOSFETs, or four n-channel MOSFETs and twopolycrystalline-silicon (poly-Si) load resistors, resulting insignificantly larger cell size (typically greater than >80 F²).Innovations which provide significant reductions in SRAM cell size whileallowing the SRAM cell to retain its favorable operating characteristicsare therefore highly desirable.

Negative differential resistance (NDR) devices have previously beenproposed for compact static memory applications. E. Goto in IRE Trans.Electronic Computers, March 1960, p. 25 disclosed an SRAM cellconsisting of two resonant tunneling diodes (RTDs) and a passtransistor. For a variety of NDR devices including RTDs, the currentfirst increases with increasing applied voltage, reaching a peak value,then decreases with increasing applied voltage over a range of appliedvoltages, exhibiting negative differential resistance over this range ofapplied voltages and reaching a minimum (“valley”) value. At yet higherapplied voltages, the current again increases with increasing appliedvoltage. Thus, the current-vs.-voltage characteristic is shaped like theletter “N”. A key figure of merit for NDR devices is the ratio of thepeak current to the valley current (PVCR). The higher the value of thePVCR, the more useful the NDR device is for variety of circuitapplications. The PVCR of RTDs is generally not high enough to make itpractical for low-power SRAM application, because in order for the RTDsin a Goto cell to have sufficient current drive, the valley current istoo large, causing large static power dissipation. In addition, RTDsrequire specialized fabrication process sequences so that the complexityof an integrated RTD/MOSFET SRAM process would be substantially higherthan that of a conventional complementary MOS (CMOS) SRAM process,resulting in higher manufacturing cost.

Accordingly, there exists a significant need for NDR devices with veryhigh (>10⁶) PVCR which can be easily integrated into a conventional CMOStechnology, for compact, low-power, low-cost SRAM.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a static random accessmemory (SRAM) cell of significantly smaller size as compared to aconventional six-transistor SRAM cell, while retaining the desirableoperating characteristics of the conventional SRAM cell withoutsignificant increase in manufacturing cost.

For achieving the object, the invention provides a semiconductor devicecomprising an n-channel insulated-gate field-effect transistor (IGFET)including a gate and source/drain electrodes, and two (preferablyn-channel) NDR-FETs each including gate and source/drain electrodes,wherein the IGFET and NDR-FET elements are formed on a common substrate,with one of the source/drain electrodes of the IGFET semiconductorelement connected to the drain electrode of a first NDR-FET and also tothe source electrode of a second NDR-FET, the gate electrode of theIGFET connected to a first control terminal, the other one of thesource/drain electrodes of the IGFET connected to a second controlterminal, the drain electrode of the first NDR-FET connected to apower-supply terminal, the source electrode of the second NDR-FETconnected to a grounded or negatively-biased terminal, and the gateelectrodes of the NDR-FETs each biased at a constant voltage. The pointof connection between the drain electrode of the first NDR-FET and thesource electrode of the second NDR-FET is the data storage node. Thissemiconductor device can function as a bistable memory cell, with accessto the data storage node provided via the IGFET.

In various embodiments, the first NDR-FET, the second NDR-FET, and theIGFET access transistor that make up the SRAM cell can be formed in twoor more semiconductor layers in a stacked configuration, therebyreducing the layout area requirements of the SRAM cell. In oneembodiment, the first NDR-FET, the second NDR-FET, and the IGFET accesstransistor can be formed in two different semiconductor layers, suchthat one of the first and second NDR-FETs and the IGFET accesstransistor overlies another of the first and second NDR-FETs and theIGFET access transistor. In another embodiment, the first and secondNDR-FETs and the IGFET access transistor can each be formed in adifferent semiconductor layer, such that the three transistors arearranged one above another (e.g., the first NDR-FET overlies the IGFETaccess transistor, and the second NDR-FET overlies the first NDR-FET).

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a static random access memory (SRAM) cellconsisting of the combination of two NDR-FET elements which form abistable latch and one n-channel enhancement-mode IGFET access element;

FIG. 2 is a plot of the current vs. storage node voltage characteristicof the bistable latch formed by the combination of two NDR-FETs as shownin FIG. 1;

FIG. 3 is a schematic cross-sectional view of an NDR-FET elementconnected to an IGFET, showing the various layers shared by the twoelements which are co-fabricated using a single process flow.

FIGS. 4A and 4B are cross-sectional views of SRAM cells consisting ofthe combination of two NDR-FET elements and one n-channelenhancement-mode IGFET access element formed in multiple stackedsemiconductor layers.

DETAILED DESCRIPTION OF THE INVENTION

A semiconductor device according a preferred embodiment of the inventionwill now be described with reference to FIGS. 1 and 2. FIG. 1 is acircuit diagram of a preferred embodiment of a static memory (SRAM) cell100 consisting of two NDR-FET elements 120, 130 which form a bistablelatch 140 and one enhancement-mode IGFET access element 110. FIG. 2 is acurrent vs. storage node voltage plot illustrating the operationalcharacteristics of the static memory cell of FIG. 1. The NDR-FET elementof the present invention is preferably of the type disclosed in thefollowing King et al. applications: Ser. No. 09/603,101 entitled “ACMOS-PROCESS COMPATIBLE, TUNABLE NDR (NEGATIVE DIFFERENTIAL RESISTANCE)DEVICE AND METHOD OF OPERATING SAME” now U.S. Pat. No. 6,512,274; andSer. No. 09/603,102 entitled “CHARGE TRAPPING DEVICE AND METHOD FORIMPLEMENTING A TRANSISTOR HAVING A NEGATIVE DIFFERENTIAL RESISTANCEMODE” now U.S. Pat. No. 6,479,862; and Ser. No. 09/602,658 entitled“CMOS COMPATIBLE PROCESS FOR MAKING A TUNABLE NEGATIVE DIFFERENTIALRESISTANCE (NDR) DEVICE” now U.S. Pat. No. 6,596,617 all of which werefiled Jun. 22, 2000 and which are hereby incorporated by reference as iffully set forth herein.

As is shown in FIG. 1, IGFET 110 is configured as a transfer gate,allowing a BIT line to be connected to a storage node under the controlof a WORD line. One of the source/drain electrodes of IGFET 110 isconnected to the storage node at potential V_(SN), the othersource/drain electrode of IGFET 110 is connected to the BIT line, andthe gate electrode of IGFET 110 is connected to the WORD line.

The source electrode of first NDR-FET 120 is connected to a groundterminal, the gate electrode of first NDR-FET 120 is supplied with firstbias voltage V_(BIAS1), the drain electrode of the NDR-FET 120 isconnected together with the source electrode of a second NDR-FET 130 tothe storage node, the gate electrode of second NDR-FET 130 is suppliedwith a second bias voltage V_(BIAS2) and the drain electrode of secondNDR-FET 130 is supplied with a positive voltage V_(DD). The currentflowing in the first NDR-FET, I_(NDR1), is dependent on the differencebetween its drain electrode potential and its source electrodepotential, V_(SN), at first increasing rapidly as V_(SN) increases,reaching a peak value when V_(SN) is equal to a critical voltageV_(NDR1), and rapidly decreasing to nearly zero as V_(SN) increasesbeyond the critical voltage V_(NDR1). The bias voltage V_(BIAS1) issufficiently high so as to ensure that first NDR-FET 120 is turned onfor values of V_(SN) ranging from 0 V (ground potential) to V_(NDR1).The current flowing in the second NDR-FET, I_(NDR2) is dependent on thedifference between its drain electrode potential and its sourceelectrode potential, V_(DD)−V_(SN), at first increasing rapidly asV_(DD)−V_(SN) increases, reaching a peak value when V_(DD)−V_(SN) isequal to a critical voltage V_(NDR2), and rapidly decreasing to nearlyzero as V_(DD)−V_(SN) increases beyond the critical voltage V_(NDR2).The bias voltage V_(BIAS2) is ideally sufficiently high so as to ensurethat second NDR-FET 130 is turned on for values of V_(DD)−V_(SN) rangingfrom 0 V (ground potential) to V_(NDR2).

Next the preferred operation of bistable latch 140 in SRAM cell 100 ofFIG. 1 will be described. FIG. 2 shows the current I_(NDR1) vs. storagenode voltage V_(SN) characteristic curve of first NDR-FET 120 obtainedby changing the storage node voltage V_(SN) in a range between 0 andV_(DD), superimposed with the current I_(NDR2) VS. storage node voltageV_(SN) characteristic curve of second NDR-FET 130. A stable operatingpoint of circuit 140 is a point where the I_(NDR1) vs. V_(SN)characteristic curve of the first NDR-FET crosses the the I_(NDR2) vs.V_(SN) characteristic curve of the second NDR-FET and additionally thecharacteristic curves I_(NDR1) and I_(NDR2) have the same gradient sign(positive or negative). (The crossing point where the characteristiccurves I_(NDR1) and I_(NDR2) have opposite gradient is not a stableoperating point.)

Therefore it is understood that circuit 140 is stable when the potentialV_(SN) at the storage node is one of two values 0 and V_(DD) as shown inFIG. 2. Accordingly, the circuit can be used as a bistable memory cellby applying a potential of one of the two values 0 and V_(DD) to the BITline as a write voltage. If the value of V_(SN) increases slightly abovethat of the low (0 V) stable operating point, current I_(NDR1) flowingin first NDR-FET 120 becomes higher than the current I_(NDR2) flowing insecond NDR-FET 130, causing the value of V_(SN) to be decreased toward 0V (ground potential), to restore it to that of the stable operatingpoint. Thus first NDR-FET 120 serves as a “pull-down” device. If thevalue of V_(SN) falls slightly below that of the high (V_(DD)) stableoperating point, the current I_(NDR2) flowing in second NDR-FET 130becomes higher than the current I_(NDR1) flowing in first NDR-FET 120,causing the value of V_(SN) to be increased toward V_(DD), to restore itto that of the stable operating point. Thus second NDR-FET 130 serves asa “pull-up” device.

IGFET 110 is controlled by the WORD line as follows: when the WORD linepotential is sufficiently high, IGFET 110 is turned on, connecting theBIT line to the storage node to allow data transfer (reading data fromthe storage node, or writing data to the storage node); when the WORDline potential is low, IGFET 110 is turned off, so that the storage nodeis electrically isolated from the BIT line. In this manner, a bistablelatch 140 is realized with two series-connected NDR-FET elements, and acompact static memory cell is obtained by integrating latch 140 with aIGFET pass transistor 110.

It should be noted that in order to achieve low standby current in theSRAM cell, the valley currents of the NDR-FETs (i.e. I_(NDR1) atV_(SN)=V_(DD) and I_(NDR2) at V_(SN)=0V) are preferably minimized, whilein order to achieve a fast read access time, the peak currents of theNDR-FETs are preferably maximized. Since the NDR-FET peak current andvalley current are controlled by the gate bias voltage applied to theNDR-FET, it is possible to achieve a very low valley current by using alower gate bias voltage when the SRAM cell is in storage mode to achievelow static power dissipation, and to achieve a very high peak current byusing a higher gate bias voltage when the SRAM cell is in read mode toachieve fast read access time. In this aspect, the NDR-FET PVCR caneffectively be enhanced by several orders of magnitude.

As previously stated, the bias voltage V_(BIAS2) should ideally besufficiently high so as to ensure that second (pull-up) NDR-FET 130 isturned on for values of V_(DD)−V_(SN) ranging from 0 V (groundpotential) to V_(NDR2). Accordingly, V_(BIAS2) should ideally be greaterthan or equal to V_(DD)+V_(T), where V_(T). is the threshold voltage ofsecond NDR-FET 130. If second NDR-FET 130 is substantially anenhancement-mode device (i.e. V_(T)>0 V), then V_(BIAS2) should begreater than V_(DD). Thus, a separate power supply voltage or a boostedsupply (such as that provided by a charge pump circuit) would be needed.It should be noted that the charge pump circuit would not consume muchpower, as it would only supply a high voltage, with negligible current.

As previously stated, the bias voltage V_(BIAS1) should be sufficientlyhigh so as to ensure that first (pull-down) NDR-FET 120 is turned on forvalues of V_(SN) ranging from 0 V (ground potential) to V_(NDR1).Therefore, V_(BIAS1) can be tied or coupled to V_(DD) if desired toreduce constraints on the aforementioned charge pump circuit.Alternatively, V_(BIAS1) can be tied to V_(BIAS2) to simplify the cellarchitecture and layout.

FIG. 3 is a schematic cross-sectional view of an NDR-FET elementconnected to an IGFET, such as would exist in the preferred embodiment.The NDR-FET and IGFET are formed to include and share many commonlayers, including at least a portion of the gate insulating film, gatefilm, interlayer insulator and metal, and hence can be readilyfabricated together on a single substrate using a single process flow.For example, a common substrate 300, a common isolation area 310 andcommon interlayer insulation layers 380 (380′) are used by NDR-FETs andIGFETs respectively. Furthermore, a single gate electrode layer is usedfor gates 360, 360′ and a single metal/contact layer 390, 390′.Source/drain regions 370, 370′ are formed at the same time, and a commonsource/drain region 375′ is shared by the NDR-FET and IGFET. This latterregion can serve as a storage node for example in the above embodiments.An NDR charge trapping layer 330 is included only within an NDR-FETregion, for the reasons set forth in the aforementioned referencedapplications. Finally, both devices can also share a gate insulationfilm 340, 340′ in some implementations.

FIG. 4A is a schematic cross-sectional view of an SRAM cell 400Aconsisting of two NDR-FET elements 411 and 412, which form a bistablelatch, and one enhancement-mode IGFET access element (“transferelement”) 420. The circuit implemented by SRAM cell 400A is describedabove with respect to SRAM cell 100 in FIG. 1. SRAM cell 400A depicts anexemplary implementation of SRAM cell 100 in which the devices formingSRAM cell 400A are formed in a stacked configuration to reduce layoutarea consumed by SRAM cell 400A in an actual integrated circuit (IC).Specifically, IGFET access element 420 is formed in a firstsemiconductor layer 401-1, and NDR-FET elements 411 and 412 are formedin a second semiconductor layer 401-2 (separated from firstsemiconductor layer 401-1 by an insulating layer 402-1 (e.g., oxidelayer)), such that NDR-FET element 411 overlies IGFET access element420.

IGFET access element 420 includes source/drain regions R5 and R6 thatare formed in first semiconductor layer 401-1, with a dielectric layerD3 formed on first semiconductor layer 401-1 between source/drainregions R5 and R6, and with a gate G3 formed on dielectric layer D3.Note that IGFET access element 420 is considered to be formed “in” firstsemiconductor layer 401-1 because source/drain regions R5 and R6 areformed in first semiconductor layer 401-1 (even through dielectric layerD3 and gate G3 are actually formed “on” first semiconductor layer401-1). NDR-FET element 411 includes a source/drain region R1 and asource/drain region R2 that is shared with NDR-FET element 412. NDR-FETelement 411 further includes a dielectric layer D1 formed on secondsemiconductor layer 401-2 between source/drain regions R1 and R2, and agate G1 formed on dielectric layer D1. Similarly, NDR-FET element 412includes source/drain regions R2 and R3, a dielectric layer D2 formed onsecond semiconductor layer 401-2 between source/drain regions R2 and R3,and a gate G2 formed on dielectric layer D2. Dielectric layers D1 and D2include charge trapping layers C1 and C2, respectively, that provide theNDR characteristics for NDR-FET elements 411 and 412 described above.Finally, a vertical interconnect (plug) 405A connects source/drainregion R6 of IGFET access element 420 with source/drain region R2 ofNDR-FET elements 411 and 412 and forms a storage node for SRAM cell400A.

As described above with respect to FIG. 1, supply voltages V_(S1) andV_(S2) (e.g., ground potential and V_(DD), respectively) are connectedacross the series-connected NDR-FET elements 411 and 412, andappropriate bias voltages V_(BIAS1) and V_(BIAS2) are supplied to gatesG1 and G2, respectively, to cause NDR-FET elements 411 and 412 toexhibit the desired bi-stable latch behavior. As further described abovewith respect to FIG. 1, gate G3 and source/drain region R5 of IGFETaccess element 420 are coupled to word (read/write) line WORD and a bit(data) line BIT, respectively, to control access and data communicationswith SRAM cell 400A.

In this manner, SRAM cell 400A provides a compact implementation of anSRAM cell. Because NDR-FET element 411 overlies (i.e., is positionedabove) IGFET access element 420, the chip area (i.e., plan view arealooking down at the chip) consumed by SRAM cell 400A is essentiallyequivalent to a 2T (two transistor) cell. Note that although bothNDR-FET elements 411 and 412 are depicted as being formed in the samesemiconductor layer 401-2 for exemplary purposes (and to simplifymanufacturing), any distribution of devices between semiconductor layers401-1 and 401-2 can be used to achieve the benefit of the stackedconfiguration. For example, IGFET access element 420 could be formed insecond semiconductor layer 401-2 and both NDR-FET elements 411 and 412could be formed in first semiconductor layer 401-1. Alternatively, IGFETaccess element 420 could be formed with one of NDR-FET elements 411 and412 in one of semiconductor layers 401-1 and 401-2, with the otherNDR-FET element being formed by itself in the other semiconductor layer.Various other configurations will be readily apparent.

Note further that additional area reduction for a 3T SRAM cell can beachived via stacking of all three devices in the cell (i.e., arrangingthe three transistors one above another). FIG. 4B is a schematiccross-sectional view of an SRAM cell 400B consisting of the two NDR-FETelements 411 and 412 and the one enhancement-mode IGFET access element420 described with respect to SRAM cell 400A in FIG. 4A. However, unlikeSRAM cell 400A, which is formed in two semiconductor layers, SRAM cell400B is formed in three semiconductor layers 401-1, 401-2, and 401-3(which are separated by insulating layers 402-1 and 402-2). Therefore,IGFET access element 420 and NDR-FET elements 411 and 412 can be formedover one another so that SRAM cell 400A effectively occupies the area ofa 1T (one transistor) cell.

For exemplary purposes, IGFET access element 420 (which includessource/drain regions R5 and R6, dielectric layer D3, and gate G3) isformed in first semiconductor layer 401-1, NDR-FET element 411 (whichincludes source/drain regions R1 and R2, dielectric layer D1 (includingcharge trapping layer C1), and gate GI) is formed in secondsemiconductor layer 401-2, and NDR-FET element 412 (which includessource/drain regions R3 and R4, dielectric layer D2 (including chargetrapping layer C2), and gate G2) is formed in third semiconductor layer401-3. Note, however, that in various other embodiments, SRAM cell 400Bcan include any distribution of NDR-FET elements 411 and 412 and IGFETaccess element 420 among semiconductor layers 401-1, 401-2, and 401-3. Avertical interconnect 405B connects the source/drain regions R2, R4, andR6 of NDR-FET element 412, NDR-FET element 411, and IGFET access element420, respectively, and forms storage node for SRAM cell 400B. BecauseNDR-FET elements 411 and 412 and IGFET access element 420 all overlieone another (i.e., are formed one over the other in a single stack),SRAM cell 400B implements the circuit of FIG. 1 in an extremelyspace-efficient manner.

While the invention has been described with reference to illustrativeembodiments, this description is not intended to be construed in alimiting sense. It will be clearly understood by those skilled in theart that foregoing description is merely by way of example and is not alimitation on the scope of the invention, which may be utilized in manytypes of integrated circuits made with conventional processingtechnologies. Various modifications and combinations of the illustrativeembodiments, as well as other embodiments of the invention, will beapparent to persons skilled in the art upon reference to thedescription. Such modifications and combinations, of course, may useother features that are already known in lieu of or in addition to whatis disclosed herein. It is therefore intended that the appended claimsencompass any such modifications or embodiments. While such claims havebeen formulated based on the particular embodiments described herein, itshould be apparent the scope of the disclosure herein also applies toany novel and non-obvious feature (or combination thereof) disclosedexplicitly or implicitly to one of skill in the art, regardless ofwhether such relates to the claims as provided below, and whether or notit solves and/or mitigates all of the same technical problems describedabove. Finally, the applicants further reserve the right to pursue newand/or additional claims directed to any such novel and non-obviousfeatures during the prosecution of the present application (and/or anyrelated applications).

1. A memory cell comprising: a first negative differential resistancefield effect transistor (NDR-FET); a second NDR-FET connected in serieswith the first NDR-FET; and an access transistor connected between adata line and a junction between the first NDR-FET and the secondNDR-FET, wherein at least one of the first NDR-FET, the second NDR-FET,and the access transistor overlies at least another of the firstNDR-FET, the second NDR-FET, and the access transistor.
 2. The memorycell of claim 1, wherein the access transistor is formed in a firstsemiconductor layer, wherein the first NDR-FET and the second NDR-FETare formed in a second semiconductor layer, the second semiconductorlayer overlying the first semiconductor layer, and wherein one of thefirst NDR-FET and the second NDR-FET overlies the access transistor. 3.The memory cell of claim 2, wherein the first NDR-FET and the secondNDR-FET share a common source/drain region.
 4. The memory cell of claim1, wherein the first NDR-FET and the second NDR-FET are formed in afirst semiconductor layer, wherein the access transistor is formed in asecond semiconductor layer, the second semiconductor layer overlying thefirst semiconductor layer, and wherein the access transistor overliesone of the first NDR-FET and the second NDR-FET.
 5. The memory cell ofclaim 4, wherein the first NDR-FET and the second NDR-FET share a commonsource/drain region.
 6. The memory cell of claim 1, wherein the firstNDR-FET and the access transistor are formed in a first semiconductorlayer, wherein the second NDR-FET is formed in a second semiconductorlayer, the second semiconductor layer overlying the first semiconductorlayer, and wherein the second NDR-FET overlies one of the first NDR-FETand the access transistor.
 7. The memory cell of claim 1, wherein thefirst NDR-FET is formed in a first semiconductor layer, wherein thesecond NDR-FET and the access transistor are formed in a secondsemiconductor layer, the second semiconductor layer overlying the firstsemiconductor layer, and wherein one of the second NDR-FET and theaccess transistor overlies the first NDR-FET.
 8. The memory cell ofclaim 1, wherein the first NDR-FET, the second NDR-FET, and the accesstransistor are arranged one above another.
 9. The memory cell of claim8, wherein the first NDR-FET is formed in a first semiconductor layer,wherein the second NDR-FET is formed in a second semiconductor layer,wherein the access transistor is formed in a third semiconductor layer,wherein the first semiconductor layer overlies the second semiconductorlayer, and wherein the second semiconductor layer overlies the thirdsemiconductor layer.
 10. The memory cell of claim 8, wherein the firstNDR-FET is formed in a first semiconductor layer, wherein the secondNDR-FET is formed in a second semiconductor layer, wherein the accesstransistor is formed in a third semiconductor layer, and wherein thethird semiconductor layer overlies the first semiconductor layer and thesecond semiconductor layer overlies the third semiconductor layer. 11.The memory cell of claim 8, wherein the first NDR-FET is formed in afirst semiconductor layer, wherein the second NDR-FET is formed in asecond semiconductor layer, wherein the access transistor is formed in athird semiconductor layer, and wherein the third semiconductor layeroverlies the first semiconductor layer and the second semiconductorlayer.
 12. A method for making a memory cell, the method comprising:forming a first negative differential resistance (NDR) field effecttransistor (FET) in series with a second NDR-FET; forming an accesstransistor for connecting a data line to a junction between the firstNDR-FET and the second NDR-FET, wherein at least one of the firstNDR-FET, the second NDR-FET, and the access transistor overlies at leastanother of the first NDR-FET, the second NDR-FET, and the accesstransistor.
 13. The method of claim 12, wherein forming the accesstransistor comprises forming the access transistor in a firstsemiconductor layer, the method further comprising: forming aninsulating layer over the access transistor; forming a secondsemiconductor layer over the insulating layer, wherein forming the firstNDR-FET in series with the second NDR-FET comprises forming the firstNDR-FET and the second NDR-FET in the second semiconductor layer suchthat one of the first NDR-FET and the second NDR-FET overlies the accesstransistor; and forming a vertical interconnect between a source/drainregion of the access transistor and the junction between the firstNDR-FET and the second NDR-FET.
 14. The method of claim 13, wherein thejunction between the first NDR-FET and the second NDR-FET comprises ashared source/drain region.
 15. The method of claim 12, wherein formingthe forming the first NDR-FET in series with the second NDR-FETcomprises forming the first NDR-FET and the second NDR-FET in a firstsemiconductor layer, the method further comprising: creating aninsulating layer over the first NDR-FET and the second NDR-FET; creatinga second semiconductor layer over the insulating layer, wherein formingthe access transistor comprises forming the access transistor in thesecond semiconductor layer such that the access transistor overlies oneof the first NDR-FET and the second NDR-FET; and forming a verticalinterconnect between a source/drain region of the access transistor andthe junction between the first NDR-FET and the second NDR-FET.
 16. Themethod of claim 15, wherein the junction between the first NDR-FET andthe second NDR-FET comprises a shared source/drain region.
 17. Themethod of claim 12, wherein forming the access transistor comprisesforming the access transistor in a first semiconductor layer, andwherein forming the first NDR-FET in series with the second NDR-FETcomprises: forming the first NDR-FET in the first semiconductor layer;creating an insulating layer over the access transistor and the firstNDR-FET; creating a second semiconductor layer over the insulatinglayer; and forming the second NDR-FET in the second semiconductor layer,wherein the second NDR-FET overlies one of the first NDR-FET and theaccess transistor.
 18. The method of claim 12, wherein forming theaccess transistor comprises forming the access transistor in a firstsemiconductor layer, and wherein forming the first NDR-FET in serieswith the second NDR-FET comprises: creating a first insulating layerover the access transistor; creating a second semiconductor layer overthe first insulating layer; forming the first NDR-FET in the secondsemiconductor layer such that the first NDR-FET overlies the accesstransistor; creating a second insulating layer over the first NDR-FET;creating a third semiconductor layer over the second insulating layer;forming the second NDR-FET in the third semiconductor layer such thatthe second NDR-FET overlies the first NDR-FET; and forming a verticalinterconnect connecting a source/drain region of the second NDR-FET, asource/drain region of the first NDR-FET, and a source/drain region ofthe access transistor.
 19. The method of claim 12, wherein forming thefirst NDR-FET in series with the second NDR-FET comprises: forming thefirst NDR-FET in a first semiconductor layer; creating a firstinsulating layer over the first NDR-FET; creating a second semiconductorlayer over the first insulating layer; forming the second NDR-FET in thesecond semiconductor layer such that the second NDR-FET overlies thefirst NDR-FET; creating a second insulating layer over the secondNDR-FET; creating a third semiconductor layer over the second insulatinglayer, wherein forming the access transistor comprises forming theaccess transistor in the third semiconductor layer such that the accesstransistor overlies the second NDR-FET; and forming a verticalinterconnect connecting a source/drain region of the access transistor,a source/drain region of the second NDR-FET, and a source/drain regionof the first NDR-FET.